Sep 27, 2010
Keynote Talk at 2010 VLSI-SoC
Subhasish Mitra, Stanford !!!
IEEE/IFIP Intl Conference on VLSI and System-on-Chip, Madrid, Spain
Stanford's Subhasish Mitra delivered a presentation at the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC) in Madrid on September 27, 2010. The keynote talk explored "Robust System Design for Scaled CMOS and Beyond."

Sep 21, 2010
Dynamic NBTI management using a 45nm multi-degradation sensor
Prashant Singh, Dennis Sylvester (UMich) et al.
2010 IEEE Custom Integrated Circuits Conference
We propose a low power unified oxide and NBTI degradation sensor designed in 45nm process node. The cell power consumption is 105 lower than a previously proposed sensor. The unified nature enables efficient reliability monitoring with reduced sensor deployment effort and area overhead. Using the sensor Dynamic NBTI Management (DNM) has been implemented for the first time. DNM trades the excess ‘reliability-margin’ present in the design, due to better than worst case operating conditions, with performance. For the typical case shown in this paper, DNM allows for an average boost of 90mV in accelerated supply voltage while bringing down the excess NBTI margin of 22.5mV to 8mV where the total NBTI budget was of 66mV.

May 17, 2010
Software Adaptation in Quality Sensitive Applications to Deal with Hardware Variability
Puneet Gupta, Aashish Pant and Mihaela van der Schaar, UCLA
Great Lakes Symposium on VLSI (GLSVLSI) 2010
In this work, the co-authors proposed a method to reduce the impact of process variations by adapting the application's algorithm at the software layer. They introduced the concept of hardware signatures as the measured post manufacturing hardware characteristics that can be used to drive software adaptation across different die.