Mar 14, 2011
Overcoming CMOS Reliability Challenges: From Devices to Circuits and Systems
Subhasish Mitra, Stanford University
Design, Automation & Test in Europe (DATE 2011)
This tutorial illustrated new opportunities in designing cost-effective robust systems of the future in light of the extreme miniaturisation of CMOS circuits, in which factors such as transient errors, device degradation, and variability induced by manufacturing and operating conditions are becoming important.

Mar 9, 2011
Post-Silicon Validation of Robust Systems
Subhasish Mitra, Stanford University
VLSI Design and Education (VDEC), D2T Symposium 2011 at University of Tokyo
Malfunctions in electronic systems have enormous consequences as systems become more complex, interconnected, and pervasive. Robust system design is required to ensure that future electronic systems perform correctly despite rising levels of complexity and increasing disturbances. Hardware failures are especially a growing concern because existing test and validation methods barely cope with today’s complexity. Moreover, at remarkably small geometries, several failure mechanisms, largely benign in the past, are becoming important. This invited talk by co-PI Mitra from Stanford focused on two recent post-silicon validation techniques for robust systems: IFRA and QED.

Mar 8, 2011
Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-Volatile Memories
Adrian Caulfied
2nd Non-Volatile Memories Workshop, San Diego
Caulfield's co-authors were Arup De, Joel Coburn, Todor Mollov, Rajesh Gupta and Steven Swanson.

Feb 23, 2011
Keynote: Making Sense of Future Embedded Sensing Platforms: Microelectronics Trends, Performance Variations, and Implications for Hardware-Software Architectures
Mani Srivastava, UCLA
8th European Conference on Wireless Sensor Networks (EWSN)
The talk in Bonn, Germany, described how variability, particularly in sleep power, is already affecting wireless sensing platforms, and how the problem will get worse in future technology nodes. The talk examined these microelectronics technology trends, and presented recent results on software mechanisms for variability-aware duty cycling from research conducted under the Expeditions project. Particularly aptly for a conference on sensing, the talk described how sensing technology at a different scale - interoceptive sensing of the inner state of the platform itself as opposed to exteroceptive sensing of the state of the surrounding world - will be a critical part of the solution and enabling wireless sensing platforms that would sense-and-adapt instead of crash-and-recover in the face of variations.

Feb 11, 2011
Coding Methods for Emerging Non-Volatile Memories
Lara Dolecek, UCLA
Information Theory and Applications Workshop 2011
Emerging non-volatile memory devices are in high demand in a variety of applications, ranging from consumer electronics to data centers. These devices offer faster data access and lower power consumption than traditional storage devices based on magnetic disks. The advent of such multi-scale opportunities for new memory technologies also carries a unique set of design challenges. One of the main concerns regarding the performance of new memory devices is that of the memory lifetime. Memory lifetime is in direct proportion to the maximum number of times a memory block can be written (programmed) or erased before the memory is rendered unusable.

Feb 7, 2011
DPC Absorbing Sets, the Null Space of the Cycle Consistency Matrix, and Tanner's Constructions
Lara Dolecek, UCLA
Information Theory and Applications Workshop 2011
Dolecek et al. introduced the cycle consistency condition, which is a necessary condition for cycles – and thus the absorbing sets that contain them – to be present in separable circulant-based (SCB) LDPC codes. This paper introduces a cycle consistency matrix (CCM) for each possible absorbing set in an SCB LDPC code.

Jan 28, 2011
Keynote: Robust Systems: From Clouds to Nanotubes
Subhasish Mitra, Stanford University
16th IEEE ACM Asia and South Pacific Design Automation Conference (ASP-DAC)
This talk in Yokohama, Japan, addressed major robust system design goals: new approaches to thorough test and validation that scale with tremendous growth in complexity; cost-effective tolerance and prediction of failures in hardware during system operation; and a practical way to overcome substantial inherent imperfections in emerging nanotechnologies.

Jan 6, 2011
Variation, Sensing and Sensibility of Energy Use in Cyber-Physical Systems
Rajesh Gupta, UC San Diego
Workshop on Sensor-Enabled Situation Awareness (SESA 2011)
This presentation took place at SESA2011 in Bangalore, India.

Jan 5, 2011
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
Parag Kulkarni, Graduate Student, UCLA
IEEE/ACM 24th International Conference on VLSI Design
The paper describes a new multiplier architecture where errors are injected at design time (i.e., by changing logic) rather than by scaling voltage. It is shown that this can save much more power at the same quality level than voltage overscaling.

Jan 5, 2011
Trading Accuracy for Power with an Underdesigned Multiplier Architecture
Puneet Gupta, UCLA
IEEE/ACM 24th International Conference on VLSI Design
Work co-authored with Parag Kulkarni and Milos Ercegovac (UCLA).

Dec 15, 2010
Invited Talk at 2010 IEEE Circuits and Systems Society CAS-Fest
Subhasish Mitra, Stanford
ICECS 2010, Athens, Greece
In mid-December 2010, Subhasish Mitra delivered an invited talk to a new forum on emerging and selected topics, CAS-FEST, in connection with ICECS 2010 in Athens, Greece. His presentation, co-authored with Kevin Brelsford, Young Moon Kim, Yanjing Li and Hsiao-Heng Kelin Lee, was on "Robust System Design to Overcome CMOS Reliability Challenges".

Dec 15, 2010
Keynote: The Variability Expedition: Addressing the Semiconductor Variability Barrier with Underdesigned and Opportunistic Computing Machines
Rajesh Gupta, UC San Diego
5th International Design & Test Workshop, Abu Dhabi
IDT 2010 was technically sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC) and technically co-sponsored by the IEEE UAE section.

Dec 15, 2010
Mitigating Variability in Near-Threshold Computing
Dennis Sylvester, University of Michigan, Ann Arbor
CAS-FEST 2010: Variation Aware Design for Nanoscale VLSI, Athens, Greece
Co-PI Dennis Sylvester, with Mingoo Seok, Gregory Chen, Scott Hanson, Michael Wieckowski, and David Blaauw, all from the University of Michigan, Ann Arbor, Electrical Engineering and Computer Science Department.

Dec 9, 2010
Towards Longer Lifetime of Emerging Memory Technologies Using Number Theory
Lara Dolecek, UCLA
IEEE Global Communications Conference 2010
Co-PI Dolecek has investigated new mathematical models for capturing and exploiting operational asymmetry in Flash memories. This work develops a family of novel coding-theoretic inspired techniques to reduce the number of excessive write operations, and demonstrates how the memory lifetime can be extended by carefully designing such provably good asymmetric error correction codes. This research work under Expeditions was presented at conferences and workshops including the 2011 IEEE Information Theory and Applications (ITA) Workshop 2011, and 2010 IEEE Globecom conference.

Dec 6, 2010
Variability Expedition
Rajesh Gupta, UC San Diego
NSF Nanoscale Science and Engineering Grantee Conference
This invited talk on the Variability Expedition was part of the National Nanotech Initiative (NNI).

Nov 11, 2010
Active learning framework for post-silicon variation extraction and test cost reduction
C. Zhuo, K. Agarwal, D. Sylvester, and D. Blaauw
IEEE/ACM International Conference on Computer-Aided Design 2010
The co-authors from the University of Michigan, Ann Arbor, proposed an active learning framework to extract process variation from measurements and reduce test cost. Several techniques are developed to model the variation. By reusing a priori knowledge from earlier wafers, the partial test can be conducted on the forthcoming wafers to achieve the required accuracy and test cost. Experimental results show that the framework can achieve an accuracy of 2-3% relative error using only ~30% test structures for two industrial processes.