| Presentations |
|
Jun 5, 2011 TrustGeM: Dynamic Trusted Environment Generation for Chip-Multiprocessors Luis A.D. Bathen, UC Irvine 4th Annual IEEE International Symposium on Hardware-Oriented Security and Trust This presentation will be part of the poster session at HOST 2011 in San Diego. The research is co-authored by Variability investigator Nikil Dutt. May 2, 2011 Keynote: Sensing and Sensibility of Energy Use in Modern Mixed-Use Buildings Rajesh Gupta, UC San Diego GLSVLSI 2011 (EPFL, Switzerland) See URL for presentation slides. Apr 25, 2011 Designing for uncertainty: Addressing process variations and aging issues in vlsi designs Puneet Gupta, UCLA IEEE International Symposium on VLSI Design, Automation and Test, 2011 At the conference in Hsinchu, Taiwan, Puneet Gupta delivered this half-day tutorial on variability and aging issues in VLSI designs. Throughout the tutorial, he gave a brief introduction to physical mechanisms of variability and aging, with an emphasis on avoiding DFM overkill, and to see where simpler approaches suffice. Click on link for the slides. Apr 15, 2011 Imperfection-Immune Digital VLSI using Carbon Nanotube Field Effect Transistors Subhasish Mitra, Stanford University Design-for-Excellence in Electronics Workshop This workshop in New York City was organized by New York University Abu Dhabi. Apr 13, 2011 Programming Support for Distributed Optimization and Control in Cyber-Physical Systems Rahul Balani, Lucas Wanner, Jonathan Friedman, Mani Srivastava (UCLA) 2nd International Conference on Cyber-Physical Systems (ICCPS) See Publications Mar 29, 2011 How Much Test Coverage Is Enough? Subhasish Mitra, Stanford University (panelist) Synopsys SNUG San Jose 2011 Mar 18, 2011 A Case for Opportunistic Embedded Sensing in Presence of Hardware Power Variability Lucas Wanner, Graduate Student, UCLA IEEE/ACM 2011 Design, Automation and Test in Europe 2011 Lucas Wanner presented his work with fellow UCLA collaborators Charwak Apte, Rahul Balani, Sadef Zahedi, Puneet Gupta, Mani Srivastava. The work shows that for currently available commercial embedded microprocessors, up to 2X lifetime benefit can be realized by making OS-level duty cycling aware of hardware variations (both process and ambient). A variation-aware duty cyling abstraction was implemented for TinyOS and tried on 10 ARM Cortex M3-based boards. (The paper, under a different title, is available in the Publications section.) Mar 18, 2011 E-RoC: Embedded Raids-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories Luis A.D. Bathen and Nikil Dutt (UC Irvine) IEEE/ACM 2011 Design, Automation and Test in Europe A paper by Luis A.D. Bathen and Nikil Dutt describing "E-RoC" -- a new approach to incorporating RAID-like redundancy policies for distributed on-chip memories -- was presented at DATE '11. This research has shown that E-RoC’s fully distributed redundant reliable memory subsystem reduces on-chip memory power consumption by up to 85% and latency up to 61% over traditional reliability approaches that use parity/cyclic hybrids for error checking and correction. Mar 18, 2011 Robust System Design Subhasish Mitra, Stanford University Nanosystem Design and Variability, EPFL (Switzerland) This talk addressed the following major robust system design goals: new approaches to thorough post-silicon validation that scale with tremendous growth in complexity; cost-effective tolerance and prediction of failures in hardware during system operation; a practical way to overcome substantial inherent imperfections in emerging nano technologies. Mar 18, 2011 On-Chip Monitoring for Self-Improvement Dennis Sylvester, University of Michigan, Ann Arbor Nanosystem Design and Variability, EPFL (Switzerland) Co-PI Sylvester discussed recent progress in on-chip variability and wearout sensing, particularly in situ approaches. One example is a demonstration of dynamic reliability management enabled by compact NBTI sensors. He also reviewed some recent chip designs from Michigan that can serve as jumping off points for variability-aware design testbeds. Mar 18, 2011 Characterization and Visualization of Power Use Variability in High Performance Platforms Rajesh Gupta, UC San Diego Nanosystem Design and Variability, EPFL (Switzerland) Variation in power use comes from various sources that include periodic processes over multiple time scales as well as random fluctuations. As a part of the Variability Expeditions we have been experimenting with methods to detect such variations in real-time as well as characterize these for identification of major sources of variability. In this talk, Gupta reviewed results from these ongoing experiments. Mar 18, 2011 Underdesigned and Opportunistic Computing Machines Puneet Gupta, UCLA Nanosystem Design and Variability, EPFL (Switzerland) Scaling of physical dimensions faster than the optical wavelengths or equipment tolerances used in the manufacturing line has led to increased process variability and low yields which make design process expensive and unpredictable. "Equivalent scaling" improvements - perhaps as much as one full technology generation - can come from looking "up" to circuit design and even to software (operating systems, compilers and applications). UCLA's Gupta argued for underdesigned and opportunistic computing which offloads some of the variability handling burden to higher layers in the hardware-software stack. With examples from multimedia and sensor processing, he showed that a fluid hardware-software interface can result in substantial improvements in power, yield and application quality. Mar 18, 2011 Cross-Layer Error Awareness for Embedded Systems Nikil Dutt, UC Irvine Nanosystem Design and Variability, EPFL (Switzerland) A holistic approach to understanding timing and its interrelationship with other QoS metrics is critical for these distributed multi-layer CPS applications. This talk described initial efforts at composing timing and reliability in a cross-layer manner and outline challenges in the context of emerging CPS applications. Mar 18, 2011 Variability in Datacenters Tajana Šimunić Rosing, UC San Diego Nanosystem Design and Variability, EPFL (Switzerland) This talk showed how the UCSD researchers could use proactive thermal management policies to reduce the environmental variability at little to no cost at the application level. The experimental results using real datacenter workloads showed that a proactive technique was able to dramatically reduce the adverse effects of temperature, and thus mitigate the aging variability, by over 60 percent. Mar 18, 2011 On the Efficacy of NBTI Mitigation Techniques John Sartori, UIUC Design, Automation & Test in Europe (DATE 2011) UIUC's John Sartori presented this paper, co-authored with Tuck-Boon Chan, Puneet Gupta, and Rakesh Kumar. The study found that guardbanding compares much more favorably against dynamic aging management techniques than previously thought. A new aging model has been made public. Mar 17, 2011 A Confidence-Driven Model for Error-Resilient Computing C-H Chen, Y Kim, Z Zhang, D Blaauw and D Sylvester, U of Michigan, Ann Arbor; H Naeimi and S Sandhu, Intel Design, Automation & Test in Europe (DATE\'11) In this paper presented at DATE 2011, the co-authors describe a confidence-driven approach to highly variable and unreliable computing platforms. The technique relies on intelligent combination of temporal and spatial redundancy to extract the benefits of both while minimizing each of their overheads. The work has been mapped to FPGA for emulation of a CORDIC processor and shows relatively low overheads with high reliability in the face of large failure rates. The work is joint with Intel and other faculty at Michigan (Zhang/Blaauw). |
