Our team is investigating abstractions for representing software-visible manifestations of hardware variations at the microarchitectural and architectural/operating system layers, and software for opportunistically exploiting variability using compiler-generated code, and run-time operating system services.

Specific goals of our team (together with Prof. Rakesh Kumar at UIUC), for this project include:

• A responsive architecture-programmer interface that extends the traditional fixed ISA specification of a computing machine to one where the ISA functionality and performance are mutable across different instances of the hardware, different invocations of an application, and within the lifetime of an application.
• Compiler strategies for managing and exploiting variability at the architecture-programmer interface, using: semantic annotation and analysis to capture/exploit application and human knowledge; “mutable” ISAs to enable generation of alternative-but-equivalent code fragments that enable execution resilience; and software-driven variability monitors that can sample/inspect behavioral changes in the hardware.
• A responsive runtime interface that provides necessary capabilities for application algorithm, just-in-time compilation, and OS services to formulate a coordinated response to variability in hardware’s specification.
• A software virtualization layer that presents a uniform programmer interface for distributed on-chip memories, and dynamic allocation and memory management techniques to handle variability-induced faults in the distributed on-chip memories.

Our objectives for the past quarter have been focused on understanding the interfaces required to enable programmer and compiler exploitation of hardware variability, and exploiting RAID-like notions to achieve a reliable software virtualization layer to manage distributed on-chip memories.

Publications:

"E-RoC: Embedded Raids-on-Chip for Low Power Distributed Dynamically Managed Reliable Memories," L.A.D. Bathen and N.D. Dutt, UC Irvine. Proc., IEEE/ACM 2011 Design, Automation and Test in Europe, 03-18-11

Milestones:

Work completed: Luis Bathen has implemented a prototype E-RoC (Embedded Raids-on-Chip) simulation platform for chip multi-processors (CMPs) deploying distributed scratch-pad memories (SPM) with a shared bus architecture. Preliminary simulation experiments on multimedia benchmarks running on a CMP architecture with distributed SPMs have shown that E-RoC’s fully distributed redundant reliable memory subsystem reduces on-chip memory power consumption by up to 85% and latency up to 61% over traditional reliability approaches that use parity/cyclic hybrids for error checking and correction.

Plans/Outlook:

Two collaborative opportunities are being pursued with the larger Expeditions team:

i. With Prof. Puneet Gupta (UCLA), we are investigating opportunities for the compiler to exploit variations in sleep power at the compiler and microarchitectural levels; and

ii. With Prof. Rakesh Kumar (UIUC), we are investigating mutation sets to withstand process-variation-induced faults in microarchitectural components.

Concept of Embedded RAIDs-on-Chip (E-RoC). E-RoC is composed of eight mutually dependent components (A through I) that are used to create a customized E-RoC Manager for the specific settings of each component. (See Publications)

Category:

Micro-Architecture / Compilers

Runtime Support

Campus:

UC Irvine

UIUC

People:

PIs: Nikil Dutt and Alex Nicolau (UC Irvine), Rakesh Kumar (UIUC); Graduate Students: Luis A.D. Bathen, Arup Chakraborty, and Marco Cesarano