The goal of this project is to study injection of functional errors (by logic changes) as opposed to parametric errors via voltage overscaling to save power for applications which are error tolerant. First goal is to propose alternative multiplier architectures for this purpose.

We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 multiplier as its building block. Our inaccurate multipliers achieve an average power saving of 31.78% − 45.4% over corresponding accurate multiplier designs, for an average error of 1.39% − 3.32%.

Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. Our approach is far more effective in trading of accuracy for power than either voltage overscaling or bitwidth truncation.

We also enhance the design to allow for correct operation of the multiplier using a correction unit, for non error-resilient applications.

Publications:

"Trading Accuracy for Power with an Underdesigned Multiplier Architecture," P. Kulkarni, P. Gupta and M. Ercegovac. Proc., IEEE/ACM International Conference on VLSI Design, 03-31-11

Plans/Outlook:

Depending on finding an interested student, we plan to extend the idea to other arithmetic units and logic in general; try out the approach on a FPGA (where the tradeoffs would differ).

In addition to the VLSI Design paper from January 2011, the team has a second paper under review at IEEE Transactions on VLSI in 2011.

(Top) Illustration of accurate mode extension; the upper path is for accurate operation while the lower path is for inaccurate operation; (bottom) Image sharpening: (a) original blurred image; (b) enhanced using accurate multiplier; (c) by inaccurate multiplier, power reduction 41.5%, SNR: 20.365dB; (d) voltage over-scaling for 30% power reduction, SNR: 9.16dB; (e) voltage over-scaling for 50% power reduction, SNR: 2.64dB; (f) by introducing errors via the adder-tree, SNR : 7.3dB

Category:

Micro-Architecture / Compilers

Campus:

UCLA

People:

PI: Puneet Gupta; Graduate Student: Parag Kulkarni (now at Altera Inc.)